1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a capability of generating chip identification information.
2. Description of the Background Art
The market of electronic commerce services provided/received through the Internet has been expanding. The electronic money service by means of IC cards is now entering the stage of spread/expansion. For these services, a higher security technology is always demanded. At the software level, an encryption technology based on a tough encryption algorithm has offered adequate security. Meanwhile, at the hardware level where a similar algorithm is physically implemented, the risk of allowing a secret key to be decrypted by an attacker such as hacker (cracker) has been pointed out. While a technique of storing an ID in a fuse or nonvolatile memory during production of a chip has conventionally been adopted, the risk of falsification of the data and/or replication of the chip itself has been pointed out.
Japanese Patent Laying-Open No. 2012-43517 and H. Fujiwara et al., “A Chip-ID Generating Circuit for Dependable LSI Using Random Address Errors on Embedded SRAM and On-Chip Memory BIST”, VLSI Circuits, 2011 disclose that, based on an address of a random defective cell which is caused by reduction of the voltage to be supplied to memory cells of a built-in SRAM, an ID specific to a chip is generated. K. Lofstrom et al., “IC Identification Circuit Using Device Mismatch”, ISSCC 2000 discloses that, based on a change of the output voltage of an inverter constituted of a resistor and a plurality of transistors connected in parallel, an ID specific to a chip is generated. The plurality of transistors have respective threshold voltages different from each other. These transistors are successively accessed and a change of the output voltage of the inverter is digitized. Accordingly, an ID specific to a chip is generated.
Y. Su et al., “A 1.6 pJ/bit 96% Stable Chip-ID Generating Circuit Using Process Variations”, ISSCC 2007 discloses a configuration where, based on data held by a cross-coupling-type NOR circuit arranged in the form of an array, an ID specific to a chip is generated. Respective threshold voltages of transistors constituting the cross-coupling-type NOR circuit are set so that they differ from each other in each cross-coupling-type NOR circuit. S. Okumura et al., “A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45×10−19”, ESSCIRS 2011 discloses that a pair of bit lines is set to a low level and thereafter a word line is raised and, based on the value of a data-holding node of a memory cell, an ID specific to a chip is generated. S. Chellappa et al., “Improved Circuits for Microchip Identification Using SRAM Mismatch”, CICC 2011 discloses a configuration where a boost voltage is applied to a word line after a pair of bit lines is set to a high level and, based on the value of a data-holding node of a memory cell, an ID specific to a chip is generated.